Privilege levels constrain protected operations through hardware execution modes, cooperating with traps and memory protection to separate software components.
A processor can execute software in modes with different authority. Control registers, protection settings, or other privileged operations require an appropriate mode; disallowed attempts cause defined exceptions.
Ordinary code therefore cannot gain unrestricted control simply by attempting the same instruction. This hardware-supported boundary differs from account authorization: an administrator’s application need not execute every instruction at the highest processor privilege.
RISC-V defines User, Supervisor, and Machine levels. Machine mode is mandatory; User and Supervisor modes support richer stacks. A conventional arrangement runs applications in U-mode, an operating system in S-mode, and underlying support in M-mode.
Implementations need not supply every combination. A simple M-only system and a platform with user and supervisor isolation offer different boundaries. Another architecture can use different names and encodings.
Calls and events transfer control through configured trap paths, with return mechanisms restoring an appropriate position and mode. Applications cannot obtain a service safely by choosing arbitrary addresses inside privileged code.
Software roles and execution modes need not map one-to-one. A virtualized operating system can run under a more privileged environment that traps or emulates its operations. Both the expected interface and the actual execution environment matter.