Program order and observed order
Compilers and processors can reorder, combine or speculate within their applicable semantics. Another CPU or device need not observe independent accesses in source order; barriers impose the relations needed for communication.
Direction and scope matter. Linux write barriers order relevant stores, while read and stronger barriers provide different guarantees. Acquire and release operations are directional too, rather than interchangeable forms of a global pause.
References: [1]
FENCE in RISC-V
RISC-V FENCE selects predecessor and successor sets from device input I, device output O, memory reads R and memory writes W. The selected sets determine the ordering rather than the instruction name alone.
These rules concern the specified memory and I/O observations. They do not automatically constrain a separate device interrupt signal. Status confirmation, notification handling and memory synchronization still follow device and platform protocols.
References: [2]
What barriers do not establish
Compiler and CPU barriers operate at different layers: constraining compiler motion alone need not constrain hardware observations. The receiving side also needs protocol-appropriate reads or acquisition; a sender-side barrier is not a universal fix.
A barrier does not make a compound operation indivisible or exclude another thread from a critical section. Cache maintenance, DMA ownership and bus-write completion have their own interfaces. The required relation should be identified before choosing a primitive.