Why one location has multiple copies
Processors can satisfy reads or buffer writes through caches while other agents cache the same location. Coherence mechanisms coordinate those copies and updates so shared-memory communication follows defined rules.
RISC-V describes coherent agents for a given location through serialized stores and eventual observation within the set. Agents can include processors, accelerators or devices, but a particular device’s membership depends on system properties.
References: [1]
Cache blocks and writeback responsibility
Caches usually manage blocks covering consecutive addresses rather than one slot per source variable. Block size and organization depend on the implementation, so source-level field boundaries need not match hardware management boundaries.
Explicit cache management is distinct from routine coherence. RISC-V separates invalidation, cleaning modified data and flushing by cleaning then invalidating. These operate on applicable cache copies, not indiscriminately on every cache in the system.
References: [1]
Coherence domains and memory ordering
Coordinating copies of one location does not guarantee source order between updates to different addresses. Publishing data and then a ready flag still needs appropriate acquire, release or barrier semantics.
CPU coherence does not establish coherence with every DMA device. A noncoherent device can see stale data or have its updates obscured by CPU caches. Linux DMA mapping and synchronization rules address this separate boundary.